VLSI Architecture for Seizure Detection Using Frontal-Lobe EEG

  

  Epilepsy is one of the most common neurological disorders, and it affects almost 1% of the population worldwide. 

    The commonly used clinical approach mainly involves manual inspection of encephalography (EEG) signals, a laborious and time-consuming process which often requires the contribution of more than one experienced neurologist .In the last decades, numerous approaches to automate this detection have been proposed and, more recently, machine learning has shown very promising performance. In VLSI work has been done by investigating the design and VLSI implementation of a machine learning algorithm that can get trained and learn particular characteristics of each patient’s brain waveforms, and later conduct patient-specific seizure detection. For both training and testing the algorithm, only signals from the frontal-lobe electrodes are used, which makes the algorithm ideal to be embedded into dry-electrode headsets, as they can only provide non-painful and reliable EEG from those electrodes.

    VLSI architecture updates has been done for hardware implementation of the algorithm that results in a significant power and resource reduction while maintaining a high seizure detection accuracy and latency. The VLSI implementation is uploaded onto a Microsemi AGL250 IGLOO FPGA and its performance are evaluated using offline recording from epilepsy patients and compared to the state of the art.